1. Field of the Invention
The present invention relates to a semiconductor memory having dummy bit lines.
2. Description of the Related Art
The density of elements or wiring lines in a memory cell array (real memory cell array) formed in a semiconductor memory is higher than that of a peripheral circuit which is provided outside the memory cell array. For this reason, at a boundary of a circumferential portion of the memory cell array and the peripheral circuit, the density (regularity) of the elements or wiring lines significantly changes. With the difference in the density, the circumferential portion is liable to be influenced by a halation in a photolithography process, which is one of fabrication processes of the semiconductor memory. With the halation, the shape of the memory cell or the wiring line in the circumferential portion is different from that of the memory cell or the wiring line in the memory cell array. The difference in shape causes a short failure or snap failure, thereby lowering the yield of the semiconductor memory.
Generally, in the semiconductor memory, in order to prevent the corruption of the element shape in the circumferential portion due to the halation, a dummy memory cell array is formed in the circumferential portion of the memory cell array. The dummy memory cell array has the same structure as that of the real memory cell array and includes dummy memory cells, a dummy word line, and a dummy bit line. The dummy memory cells are shape dummies and do not store write data. For this reason, typically, the dummy word line and the dummy bit line are connected to a precharge voltage, which is a normal voltage of a bit line.
In Japanese Unexamined Patent Application Publication No. 2000-339979, a virtually grounded nonvolatile semiconductor memory having dummy memory cells is disclosed. In the semiconductor memory, a dummy bit line connected to each dummy memory cell temporarily receives a negative voltage via a transistor so as to increase a threshold voltage of the dummy memory cell. Accordingly, a read margin of a real memory cell adjacent to the dummy memory cell is prevented from being lowered. However, after the threshold voltage of the dummy memory cell is increased, the dummy bit line becomes in a floating state. A bit line which continues to be in the floating state for a long time may change in accordance with the change in voltage of an adjacent wiring line (crosstalk). For this reason, a malfunction may occur due to the crosstalk.
In Japanese Patent Unexamined Patent Application Publication No. 10-144889, a DRAM in which contacts for connecting dummy bit lines, which are fixed to a precharge voltage, to dummy memory cells are not formed is disclosed. In the DRAM, the dummy bit lines are prevented from being connected to capacitors of the real memory cells to be electrically short-circuited via capacitors of the dummy memory cells, thereby preventing a leak failure. However, the dummy memory cells are basically formed so as to prevent the halation. For this reason, if the shape of the pattern of the dummy memory cells changes, the effect on the halation may be lowered.
In the semiconductor memory, such as the DRAM, or the like, there are many cases in which the dummy bit lines are fixed to the precharge voltage, that is, a resetting voltage of real bit lines through which data is output/input. On the other hand, with a minute element structure, the distance between adjacent wiring lines and the distance between the wiring lines and the elements tend to be small. For this reason, between the dummy bit lines and other wiring lines or between the dummy bit lines and the elements (transistors), the leak failure may easily occur. In addition, with the minute element structure, the cause for this type of the leak failure (failure places) may change even when the fabricating condition of the semiconductor changes somewhat. For this reason, the cause for the leak failure generated in the dummy bit lines may change between wafers in a lot or may change according to the position of a semiconductor memory chip in a wafer, as well as between fabricating lots.
The leak failure increases a standby current and thus lowers the yield. In particular, the specification of the standby current is further rigid to a semiconductor memory that is mounted on a hand-held terminal powered by a battery. In such a semiconductor memory, due to the increase in the standby current, the yield may be significantly lowered.